Comparators are well known in the art. A comparator is a circuit which compares one input signal with at least another input signal and outputs a binary signal based on the result of the comparison. In the case of an analog comparator, the two or more input signals to be compared are generally analog in nature. What is meant here by an analog signal is one that can have one of a continuum of amplitude values at any given point in time. In many applications, it is desirable to provide a binary output signal indicating when an input signal is above or below a predefined reference level. In this scenario, a substantially fixed reference voltage is applied to one of the inputs of the comparator, and the other input of the comparator receives the input signal to be compared. The output signal generated by the comparator will be a binary signal representing whether the input signal is greater than or less than the reference voltage level.
Certain input/output (I/O) interface applications, including, for example, gunning transistor logic (GTL), high-speed transceiver logic (HSTL), and series stub terminated logic (SSTL), require comparator circuits which compare an input signal against a reference signal in order to recover transmitted data carried in the input signal. In such comparator circuits, it is generally necessary to have a substantially low pulse width distortion over a desired range of process, voltage and/or temperature (PVT) variations to which the comparator circuits may be subjected in order to reliably recover the data without errors and with adequate margin.
One known method for reducing pulse width distortion in a comparator is to increase a tail current in a differential amplifier of the comparator. Increasing the tail current in the differential amplifier serves, at least in part, to increase a slew rate of the amplifier, thereby reducing the amount of time that the amplifier spends in a switching region of a logic stage which may be coupled to an output of the amplifier. However, increasing the tail current also increases overall power consumption in the comparator and is thus undesirable. Known comparator circuit arrangements inherently lack a mechanism for controlling a signal swing of the output of the differential amplifier so that the output is substantially centered around a switching point of a logic stage which may be connected to the amplifier. Furthermore, a large signal swing on the output of the differential amplifier can often result in an increase in the amount of jitter at the comparator output induced by the differential amplifier.
A need exists, therefore, for an improved comparator circuit having reduced pulse width distortion, which does not suffer from one or more of the problems exhibited by conventional comparator circuits.